TNETX3150A datasheet(51/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DRAM flag register at 0x00D8

BIT

DRAMACT

Reserved

DRAMFLAG

BIT

NAME

FUNCTION

DRAMACT

DRAM test access. DRAMACT contains the status of a DRAM test access READ or WRITE. When this

activity bit is high, the DRAM access is being performed. When this bit is low, the DRAM access has

completed. After a DRAM test access buffer is read, the user should detect a falling edge on this bit before

proceeding to use the accessed data.

6–4

Reserved

3–0

DRAMFLAG

DRAM flag field. DRAMFLAG holds a value that maps to the flag field of a DRAM buffer when accessed in

DRAM test-access mode.

DRAM addr register at 0x00D9–0x00DB

BIT

R/W

DRAMADDRESS

BIT

NAME

FUNCTION

R/W

DRAM test access read/write. R/W determines whether the contents of channel 0’s FIFO, DRAM data, and

DRAMFLAG are read from DRAM or written to DRAM. When high, the write operation is performed. When

low, a read operation is performed.

22–0

DRAMADDRESS

DRAM starting word address. DRAMADDRESS is a 23-bit DRAM address marking the starting word

location for a DRAM test access buffer operation.

The DRAM address space (as used in this register) is not flat. It is partitioned in the following manner:

BIT

Reserved

DX02

RAS

DX02

CAS

DX01

RAS

DX01

CAS

DX00

RAS

DX00

CAS

Row address (8 bits)

Column address (8 bits)

BIT

NAME

FUNCTION

Reserved

DX02

Extended address bit 2 (RAS)

DX02

Extended address bit 2 (CAS)

DX01

Extended address bit 1 (RAS)

DX01

Extended address bit 1 (CAS)

DX00

Extended address bit 0 (RAS)

DX00

Extended address bit 0 (CAS)

15–8

RAS

Row address for DRAM (most-significant bit = bit 15)

7–0

CAS

Column address for DRAM (most-significant bit = bit 7)

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