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MAX1102 데이터시트(PDF) 4 Page - Maxim Integrated Products |
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MAX1102 데이터시트(HTML) 4 Page - Maxim Integrated Products |
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4 / 16 page ![]() 8-Bit CODECs 4 _______________________________________________________________________________________ Note 1: MAX1102/MAX1104 tested with VDD = +3V. MAX1103 tested with VDD = +5V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. Note 3: Gain error calculation is referenced to the ideal FS output. Gain error for the MAX1102/MAX1103 also includes reference ini- tial accuracy error. Note 4: Wake-up time is the time it takes for the DAC output to settle to within ±1/2 LSB of the FS value after a power-up command. Note 5: Output settling time is measured by taking the DAC from code 00hex to FFhex. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY REQUIREMENTS MAX1102 2.7 3.6 MAX1103 4.5 5.5 Supply Voltage VDD MAX1104 2.7 5.5 V ADC on (25ksps), DAC off 0.25 0.5 Supply Current ICC ADC off, DAC on (VDD = +5.5V) 0.4 0.66 mA Standby Current ADC off, DAC off, clock off, reference on 18 35 µA Full Shutdown Current ADC off, DAC off, clock off 1 µA ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k Ω, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25°C unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Up to Reset Complete t9 40 µs CS Rise-to-DOUT = High-Z t10 40 ns CS Fall-to-DOUT Valid t11 RDOUT = 3k Ω, CDOUT = 50pF 60 ns CS Fall-to-SCLK Rise t3 15 ns SCLK Fall-to-CS Rise t8 25 ns DIN-to-SCLK Setup Time t4 10 ns DIN-to-SCLK Hold Time t5 15 ns SCLK Fall to DOUT Valid t6 RDOUT = 3k Ω, CDOUT = 50pF 70 ns SCLK Maximum Frequency fSCLK 6 MHz SCLK Pulse Width High tCH 60 ns SCLK Pulse Width Low tCL 70 ns TIMING CHARACTERISTICS (Figures 4a and 4b) (VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10k Ω, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25°C unless otherwise noted.) |
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