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CY2071ASC 데이터시트(PDF) 6 Page - Cypress Semiconductor

부품명 CY2071ASC
상세설명  Single-PLL General-Purpose EPROM Programmable Clock Generator
PDF  8 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2071ASC 데이터시트(HTML) 6 Page - Cypress Semiconductor

  CY2071ASC Datasheet HTML 1Page - Cypress Semiconductor CY2071ASC Datasheet HTML 2Page - Cypress Semiconductor CY2071ASC Datasheet HTML 3Page - Cypress Semiconductor CY2071ASC Datasheet HTML 4Page - Cypress Semiconductor CY2071ASC Datasheet HTML 5Page - Cypress Semiconductor CY2071ASC Datasheet HTML 6Page - Cypress Semiconductor CY2071ASC Datasheet HTML 7Page - Cypress Semiconductor CY2071ASC Datasheet HTML 8Page - Cypress Semiconductor  
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CY2071A
Document #: 38-07139 Rev. *A
Page 6 of 8
Switching Characteristics, Industrial 3.3V[8]
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range
3.3V operation
15-pF load
CY2071AI
12.50
[80 MHz]
2000
[500 kHz]
ns
CY2071AFI
15.0
[66.6 MHz]
2000
[500 kHz]
ns
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
0.8
1
%
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz
≤ f
OUT ≤ 50 MHz)
350
500
ps
t1C
Clock Jitter[9]
Peak-to-peak period jitter (fOUT > 50 MHz)
250
350
ps
Output Duty Cycle
Duty cycle[10, 11] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
45%
50%
55%
Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
40%
50%
60%
t3
Rise time[9]
Output clock rise time
1.5
2.5
ns
t4
Fall time[9]
Output clock fall time
1.5
2.5
ns
t5
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
0.5
ns
Switching Waveforms
All Outputs Duty Cycle and Rise/Fall Time
2071A–3
OUTPUT
t3
t4
t2
t1
2.4V
0.4V
0.4V
2.4V
VDD
0V
Output-Output Clock Skew
2071A–4
OUTPUT
OUTPUT
t5



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