853006AG

www.icst.com/products/hiperclocks.html

REV. A AUGUST 18, 2004

8

Integrated

Circuit

Systems, Inc.

ICS853006

Figure 1 shows an example of the differential input that can be

wired to accept single ended levels. The reference voltage level

V

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

50

Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion.

Figures 2A and 2B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

The C1 capacitor should be located as close as possible to the

input pin.

PCLK

nPCLK

VBB

C1

0.1u

CLK_IN

VCC