OPA561

SBOS206E − DECEMBER 2001 − REVISED FEBRUARY 2007

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2

Supply Voltage, V− to V+

16V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Voltage Range

(V−) −0.4V to (V+) + 0.5V

. . . . . . . . . . . . . . .

Input Shutdown Voltage

(V−) −0.4V to (V−) + 0.5V

. . . . . . . . . . . .

Operating Temperature

−40

°C to +125°C

. . . . . . . . . . . . . . . . . . . . .

Storage Temperature

−65

°C to +150°C

. . . . . . . . . . . . . . . . . . . . . . .

Junction Temperature

+150

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods

may degrade device reliability. These are stress ratings only, and

functional operation of the device at these or any other conditions

beyond those specified is not supported.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas In-

struments recommends that all integrated circuits be han-

dled with appropriate precautions. Failure to observe prop-

er handling and installation procedures can cause

damage.

ESD damage can range from subtle performance

degradation

to

complete

device

failure.

Precision

integrated circuits may be more susceptible to damage

because very small parametric changes could cause the

device not to meet its published specifications.

PRODUCT

PACKAGE-LEAD

PACKAGE

DESIGNATOR

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

OPA561PWP

HTSSOP-20

PWP

−40

°C to +125°C

OPA561

OPA561PWP

Rails, 70

OPA561PWP

HTSSOP-20

PWP

−40

°C to +125°C

OPA561

OPA561PWP/2K

Tape and Reel, 2000

ELECTRICAL CHARACTERISTICS

At TCASE = +25°C, VS = 15V, load connected to VS/2, and E/S enabled, unless otherwise noted.

OPA561

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

OFFSET VOLTAGE

VS = 12V

Input Offset Voltage

VOS

VCM = 0V

±1

±20

mV

vs Temperature

dVOS/dT

±50

µV/°C

vs Power Supply

PSRR

VCM = 0V, VS = 7V to 16V

25

150

µV/V

INPUT BIAS CURRENT(1)

Input Bias Current

IB

VCM = 0V

10

100

pA

Input Offset Current

IOS

VCM = 0V

10

100

pA

NOISE

Input Voltage Noise Density

en

f = 1kHz

83

nV/

√Hz

f = 10kHz

32

nV/

√Hz

f = 100kHz

14

nV/

√Hz

Current Noise

in

f = 1kHz

4

fA/

√Hz

INPUT VOLTAGE RANGE

Common-Mode Voltage Range

VCM

Linear Operation

(V−) − 0.1

(V+) − 3

V

Common-Mode Rejection Ratio

CMRR

VS = 15V, VCM = (V−) − 0.1V to (V+) − 3V

70

80

dB

INPUT IMPEDANCE

Differential

1.8

S 1011 || 10

Ω || pF

Common-Mode

1.8

S 1011 || 18.5

Ω || pF

OPEN-LOOP GAIN

Open-Loop Voltage Gain

AOL

VO = 10VPP, RL = 5Ω

80

100

dB

FREQUENCY RESPONSE

Gain-Bandwidth Product

GBW

RL = 5Ω

17

MHz

Slew Rate

SR

G = 1, 10V Step, RL = 5Ω

50

V/

µs

Full-Power Bandwidth

G = +2, VOUT = 10Vp-p

1

MHz

Settling Time:

±0.1%

G = −1, 10V Step

1

µs

Total Harmonic Distortion + Noise

THD+N

f = 1kHz, RL = 5Ω, G = +2, VO = 10VPP

0.02

%

f = 1MHz

3

%

Not Recommended for New Designs