PCF8833 datasheet(18/112 Pages) PHILIPS

18 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

6.2.7

READ DISPLAY STATUS

The Read Display Status (RDDST) command returns a

32-bit display status information and can be accessed

when the PCF8833 is in normal Display mode (see

Section 6.2.11), in partial Display mode (see

Section 6.2.23) or in Sleep_IN mode; see Section 6.2.8.

The input and output data format is as follows: After the

command byte 09H is sent, the read starts with one

dummy clock cycle followed by the 4 status bytes (see

Fig.48).

When less than 33 read clock cycles are sent in Serial

mode the status read must be interrupted by a hardware

reset or a rising edge of SCE.

The definition of the display status bits is given in Table 11.

Table 12 Read display status register bits

Table 13 RDDST data format for Serial mode

Table 14 RDDST data format for Parallel mode

D/C

6543210

DEFAULT

0001001

09H

BIT

D/C

76543210

DEFAULT

(S)DIN

000001001

09H

(S)DOUT

−

X (only one dummy clock cycle, not a full byte)

(S)DOUT

−

D31

D30

D29

D28

D27

D26

−

D22

D21

D20

D19

D18

D17

D16

−

D15

D13

D12

D11

D10

−

00000000

D/C

6543210

DEFAULT

0001001

09H

XXXXXXX

D31

D30

D29

D28

D27

D26

D22

D21

D20

D19

D18

D17

D16

D15

D13

D12

D11

D10

0000000

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