Silan

Semiconductors

SC7313

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

Rev: 1.1

2002.02.26

7

APPLICATION NOTES

1. I

interface, consisting of the two lines SDA and SCL(pull-up resistors to positive supply voltage must be connected).

2. DATA VALIDITY

As shown in Figure 17, the data of the SDA line must be stable during the high period of the clock. The HIGH

and LOW state of the dtat line can only change when the clock signal on the SCL line is LOW.

SDA

SCL

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

3. START AND STOP CONDITIONS

As shown in Figure 18, a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The

stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

//

//

SCL

SDA

start

stop

BUS

4. BYTE FORMAT

Every byte transferred on the SDA line must obtain 8 bits. Each byte must be followed by the an acknowledge

bit. The MSB is transferred first.