84021AY

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 7, 2003

1

Integrated

Circuit

Systems, Inc.

ICS84021

The ICS84021 is a general purpose, Crystal-to-

LVCMOS/LVTTL High Frequency Synthesizer

and a member of the HiPerClockS™ family of

High Performance Clock Solutions from ICS. The

ICS84021 has a selectable TEST_CLK or crys-

tal input. The VCO operates at a frequency range of 620MHz

to 780MHz. The VCO frequency is programmed in steps

equal to the value of the input reference or crystal frequency.

The VCO and output frequency can be programmed using

the serial or parallel interface to the configuration logic. The

low phase noise characteristics of the ICS84021 make it an

ideal clock source for Gigabit Ethernet, SONET, Fibre Chan-

nel 1 and 2, and Infiniband applications.

• 2 LVCMOS/LVTTL outputs

• Selectable crystal oscillator interface

or LVCMOS/LVTTL TEST_CLK

• Output frequency range: 103.3MHz to 260MHz

• Crystal input frequency range: 14MHz to 40MHz

• VCO range: 620MHz to 780MHz

• Parallel or serial interface for programming counter

and output dividers

• RMS period jitter: 4.3ps (typical) (N ÷ 4, V

• RMS phase jitter at 155.52MHz, using a 38.88MHz crystal

(12KHz to 20MHz): 2.88ps (typical)

Phase noise: 155.52MHz

Offset

Noise Power

100Hz ................. -93.7 dBc/Hz

1KHz ............... -111.3 dBc/Hz

10KHz ............... -120.4 dBc/Hz

100KHz ............... -125.1 dBc/Hz

• Full 3.3V or mixed 3.3V core/2.5V or 1.8V supply voltage

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

XTAL2

TEST_CLK

XTAL_SEL

S_LOAD

S_DATA

S_CLOCK

MR

M5

M6

M7

M8

N0

N1

nc

GND

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

ICS84021

HiPerClockS™

ICS

OSC

OE0

OE1

VCO_SEL

XTAL_SEL

TEST_CLK

XTAL1

XTAL2

S_LOAD

S_DATA

S_CLOCK

nP_LOAD

M0:M8

N0:N1

VCO

PLL

Q0

Q1

TEST

CONFIGURATION

INTERFACE

LOGIC

÷ M

0

1

0

1

PHASE DETECTOR

÷3

÷4

÷5

÷6

MR