GS2965 datasheet(21/41 Pages) SEMTECH

21 / 41 page

GS2965 Multi-Rate SDI Reclocker with Equalization &

De-emphasis

Data Sheet

52462 - 4

July 2012

21 of 41

Proprietary & Confidential

NOTE: Changing the de-emphasis setting will vary both V1 & V2 (see Figure 4-2).

The DEn_EN pins are multiplexed with the serial host interface pins. The DEn_EN

functionality is enabled when pin HIF is tied HIGH, as shown in Table 4-7:

Figure 4-2: De-emphasis Waveform

4.10 Automatic and Manual Data Rate Selection

The GS2965 can be configured to manually lock to a specific data rate or automatically

search for and lock to the incoming data rate. The default configuration is AUTO mode.

This can be changed via the host interface.

In AUTO mode, the SS[1:0] registers become read only, and the bit pattern indicates the

data rate at which the PLL is currently locked to (or previously locked to). The search

algorithm cycles through the data rates and starts over if that data rate is not found (see

Figure 4-3).

A “search algorithm” cycles through the supported data rates until lock is achieved, as

shown in Figure 4-3 below.

Table 4-7: DEn_EN Pins Multiplexed

Function

SDO/DE0_EN

Active-high logic input to enable de-emphasis for high-speed input

channel 0.

SCK/DE1_EN

Active-high logic input to enable de-emphasis for high-speed input

channel 1.

-V1

-V2

Tx signal after de-emphasis

11110000 pattern

268

269

270

271

272

273

274

275

-0.6

-0.4

-0.2

0.2

0.4

0.6

De-emphasis (dB)

=20 log (V1/V2)

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