| 전자부품 데이터시트 검색엔진 |
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PC87591E 데이터시트(PDF) 76 Page - National Semiconductor (TI) |
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PC87591E 데이터시트(HTML) 76 Page - National Semiconductor (TI) |
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76 / 437 page ![]() 4.0 Embedded Controller Modules (Continued) www.national.com 76 Revision 1.07 4.1.6 Normal Read Bus Cycle A read bus cycle starts at T1; at this point, the address is placed on the address bus, SELn (or SELIO) is activated and WR0-1 are inactive, indicating that this is a read bus cycle. The RD signal is activated on the first TIW or T2 (when there are no TIW cycles). At the end of T2, the BIU samples the data on D0-7 or D0-15, according to BW signal in SZCFGn register. After T2, the number of Thold cycles specified by HOLD in SZCFGn register (may be 0) is added. SELn and RD are deactivated on the first Thold cycle. The address remains valid until the end of the last Thold cycle. CLK A0-19 SEL0-1, D0-15 RD WR0-1 Normal Read Late Write Normal Read T1 T2 T1 T2 T1 T2 Bus State In Out In BST0-2 SELIO Figure 16. Late Write Bus Cycle Between Normal Read Bus Cycles with 0 Wait CLK A0-19 SELn D0-15 RD WR0-1 Bus State T1 TIW T2 Thold BST0-2 Figure 17. Late Write Bus Cycle with 1 Internal Wait and 1 Hold Out |
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