PCM1802

SLES023B – DECEMBER 2001 – REVISED MARCH 2002

4

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noted)

TEST CONDITIONS

PCM1802DB

UNIT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

24

bits

DATA FORMAT

Audio data interface format

Left justified, I2S,

right justified

Audio data bit length

20, 24

bits

Audio data format

MSB first, 2s complement

fS

Sampling frequency

16

44.1

96

kHz

256 fS

4.096

11.2896

24.576

System clock frequency

384 fS

6.144

16.9344

36.864

MHz

System clock frequency

512 fS

8.192

22.5792

49.152

MHz

768 fS

12.288

33.8688

INPUT LOGIC

VIH

See Note 1

2

VDD

VIL

See Note 1

Input logic level

0

0.8

VDC

VIH

See Note 2

Input logic level

2

5.5

VDC

VIL

See Note 2

0

0.8

IIH

See Note 3

VIN = VDD

±10

IIL

See Note 3

Input logic current

VIN = 0 V

±10

A

IIH

See Note 4

Input logic current

VIN = VDD

65

100

µA

IIL

See Note 4

VIN = 0 V

±10

OUTPUT LOGIC

VOH

See Note 5

Output logic level

IOUT = –1 mA

2.8

VDC

VOL

See Note 5

Output logic level

IOUT = 1 mA

0.5

VDC

DC ACCURACY

Gain mismatch channel-to-channel

±1

±4

%FSR

Gain error

±2

±6

%FSR

Bipolar zero error

LCF bypass (see Note 6)

±2

%FSR

NOTES:

1. Pins 9–11: FSYNC, LRCK, BCK (Schmitt-trigger input, in slave mode)

2. Pins 7–8, 15–20: PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, 5-V tolerant).

3. Pins 9–11, 15: FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode), SCKI (Schmitt-trigger input).

4. Pins 7–8, 16–20: PDWN, BYPAS, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-k

Ω typical pulldown

resistor).

5. Pins 9–12: FSYNC, LRCK, BCK (in master mode), DOUT

6. Low cut filter