DESCRIPTION

s Guaranteed AC performance over temperature

and voltage:

• < 20ps within-device skew

• < 225ps rise/fall times

s Low jitter design:

• Cycle-to-cycle: < 1ps (rms)

• Total jitter: < 10ps (pk-pk)

s Low voltage 2.5V and 3.3V supply operation

s Four differential 100k LVPECL outputs

s Wide operating temperature range: –40

s Includes a 2:1 MUX select input

s Accepts single-ended TTL/CMOS inputs and

provides four LVPECL outputs

s Available in 16-pin (3mm

××××× 3mm) MLF™ package

FEATURES

2.5V/3.3V TWO INPUT , 1GHz

LVTTL/CMOS-TO-LVPECL

1:4 FANOUT BUFFER/TRANSLATOR

Precision Edge™

SY89834U

APPLICATIONS

s Processor clock distribution/translation

s SONET clock distribution/translation

s Fibre Channel clock distribution/translation

s Gigabit Ethernet clock distribution/translation

s Single-ended ASIC-to-differential communication

IC signal translation

1

Rev.: C

Amendment: /0

Issue Date:

February 2003

The SY89834U is a high-speed, 2GHz LVTTL/CMOS-to-

LVPECL fanout buffer/translator optimized for high-speed

ultra-low skew applications. The input stage is designed to

accept two single-ended LVTTL/CMOS compatible signals

that feed into a 2:1 MUX. The selected input is translated

and distributed as four differential 100K compatible LVPECL

outputs. Within device skew is guaranteed to be less than

20ps over supply voltage and temperature.

The single-ended input buffers accept TTL/CMOS logic

levels. The internal threshold of the buffers is defined as

The SY89834U is a part of Micrel's high-speed Precision

Edge™ family. For applications that require a different I/O

combination, consult Micrel's website at

and choose from a comprehensive product line of high-

speed, low-skew fanout buffers, translators and clock

generators.

FUNCTIONAL BLOCK DIAGRAM

Precision Edge is a trademark of Micrel, Inc.

IN1

(LVTTL/CMOS)

(LVTTL/CMOS)

2 Single-Ended

Clock/Data Inputs

IN2

Q0

/Q0

Q1

/Q1

4 Differential

LVPECL Outputs

Q2

/Q2

Q3

/Q3

Q

D

EN

SEL

1

0

MUX

Precision Edge™