13

* VT86C926 supports the control and status registers of DP8390 except those explained as follows.

* VT86C926 supports all page 1 registers. Only part of Page 2 is supported.

* VT86C926 supports Early Transmit Underrun (ETUN)

* VT86C926 supports most of page 0 registers.

* The meaning and use of 01H (CLAD0) and 02H (CLAD1) of page 0 is altered.

* The 06H (FIFO port) of page 0 is not supported.

* The following control/status bits in page 0 are not supported:

--

(D3,D4,D5) == (0,1,1) of CR (00H) : Send Packet Command (RD0 - RD2)

--

D1 of DCR: Byte Order Select (BOS)

--

D2 of DCR: Long Address Select (LAS)

--

D4 of DCR: Auto-initialize Remote (ARM)

--

D5, D6 of DCR: FIFO Threshold Select (FT0 and FT1)

--

D4 of TCR: Collision Offset Enable (OFST)

--

D5 of TSR: FIFO Underrun (FU)

--

D7 of TSR: Out of Window Collision (OWC)

--

D3 of RSR: FIFO Overrun (FO)

The

VT86C926

provides

an

one

level

power

down

mode.

The

BIOS

or

Network OS

device driver can configure Register A to diagnostic mode

then

set

the

Power-on

bit

of

the

diagnostic

port

to

"on."

When

the

VT86C926 is in Power down mode, all power to the analog port is cut off

and the chip clock is stopped.

Other registers are read only.

Only the

diagnostic port is read-writeable.