UT6264CSCL-70 datasheet(6/10 Pages) ETC

6 / 10 page

UTRON

UT6264C

Rev. 1.1

8K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919



DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃)

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP. MAX. UNIT

Vcc for Data Retention

VDR

CE ≧ VCC-0.2V or CE2 ≤ 0.2V

2.0

5.5

-L

µA

Data Retention Current

IDR

Vcc=2V

CE ≧VCC-0.2V or CE2 ≤ 0.2V

-LL

0.5

µA

Chip Disable to Data

Retention Time

tCDR

See Data RetentionWaveforms

(below)

Recovery Time

tRC*

tRC* = Read Cycle Time

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (

CE controlled)

Data Retention Mode

VDR ≧ 2V

CE1 ≧ VCC-0.2V

Vcc

VIH

VCC

CE1

tCDR

Low Vcc Data Retention Waveform (2) (CE2 controlled)

Data Retention Mode

VDR ≧ 2V

Vcc

VCC

tCDR

CE2 ≦ 0.2V

VIL

CE2

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