CY7C68000
PRELIMINARY
Document #: 38-08016 Rev. *E
Page 13 of 14
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
13.0
Quad Flat Package No Leads (QFN)
Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good ther-
mal bond to the circuit board. A Copper (Cu) fill is to be de-
signed into the PCB as a thermal pad under the package. Heat
is transferred from the TX2 through the device’s metal paddle
on the bottom side of the package. Heat from here, is conduct-
ed to the PCB at the thermal pad. It is then conducted from the
thermal pad to the PCB inner ground plane by an array of via.
A via is a plated through hole in the PCB with a finished diam-
eter of 13 mil. The QFN’s metal die paddle must be soldered
to the PCB’s thermal pad. Solder mask is placed on the board
top side over each via to resist solder flow into the via. The
mask on the top side also minimizes outgassing during the
solder reflow process.
For further information on this package design please refer to
the application note “Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology.” This application note
can be downloaded from AMKOR’s web site from the following
URL http://www.amkor.com/products/notes_papers/MLFApp
Note.pdf. The application note provides detailed information
on board mounting guidelines, soldering flow, rework process,
etc.
Figure 13-1 below display a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that “No Clean”, type 3
solder paste is used for mounting the part. Nitrogen purge is
recommended during reflow.
Figure 13-2 is a plot of the solder mask pattern image of the assembly (darker areas indicate solder).
EZ-USB TX2 is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Figure 13-1. Crosssection of the Area Underneath the QFN Package
Figure 13-2. Plot of the Solder Mask (White Area)
0.017” dia
Solder Mask
Cu Fill
Cu Fill
PCB Material
PCB Material
0.013” dia
Via hole for thermally connecting the
QFN to the circuit board ground plane.
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
