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ESDA6V1W5 데이터시트(PDF) 3 Page - STMicroelectronics

부품명 ESDA6V1W5
상세설명  QUAL TRANSIL ARRAY FOR ESD PROTECTION
PDF  7 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ESDA6V1W5 데이터시트(HTML) 3 Page - STMicroelectronics

  ESDA6V1W5 Datasheet HTML 1Page - STMicroelectronics ESDA6V1W5 Datasheet HTML 2Page - STMicroelectronics ESDA6V1W5 Datasheet HTML 3Page - STMicroelectronics ESDA6V1W5 Datasheet HTML 4Page - STMicroelectronics ESDA6V1W5 Datasheet HTML 5Page - STMicroelectronics ESDA6V1W5 Datasheet HTML 6Page - STMicroelectronics ESDA6V1W5 Datasheet HTML 7Page - STMicroelectronics  
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The ESDA family has been designed to clamp fast
spikes like ESD. Generally the PCB designers
need to calculate easily the clamping voltage VCL.
This is why we give the dynamic resistance in
addition to the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
VCL = VBR + Rd IPP
Where Ipp is the peak current through the ESDA cell.
DYNAMIC RESISTANCE MEASUREMENT
The short duration of the ESD has led us to prefer
a more adapted test wave, as below defined, to the
classical 8/20
µs and 10/1000µs surges.
2.5
µs duration measurement wave.
As the value of the dynamic resistance remains
stable for a surge duration lower than 20
µs, the
2.5
µs rectangular surge is well adapted. In addition
both rise and fall times are optimized to avoid any
parasitic phenomenon during the measurement of
Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
2µs
tp = 2.5µs
t
I
Ipp
ESDA6V1W5
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