Connection Diagram

TSSOP Package Pin Description

Pin Name

Pin #

Type

Description

CLKI/O+

6

I/O

True (Positive) side of the differential clock input.

CLKI/O−

7

I/O

Complementary (Negative) side of the differential clock input.

OE

2

I

OE; this pin is active Low. When High, this pin forces all CLK

OUT

pins High. When Low, CLK

either the CrdCLK

the logic level at the DE pin. This pin has a weak pullup device to

V

DE

11

I

DE; this pin is active LOW. When Low, this pin enables the

CardCLK

the state of the CLK

V

CLK

OUT

13, 15, 17, 19, 21,

23

O

6 Buffered clock (CMOS) outputs.

CrdCLK

IN

9

I

Input clock from Card (CMOS level or TTL level).

V

CC

16, 20, 24

Power

V

or use separate power supplies). No special power sequencing

required. Either V

apply both power supplies.

GND

1, 12, 14, 18, 22

Ground

GND

V

CCA

4

Power

Analog V

separate power supplies). No special power sequencing required.

Either V

power supplies.

GNDA

5, 8

Ground

Analog Ground (Internally separate from Ground must be connected

externally).

NC

3, 10

No Connects

DS101082-2

Order Number DS92CK16TMTC

See NS Package Number MTC24

www.national.com

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