M68AF511AL70MC6T datasheet(8/18 Pages) STMICROELECTRONICS

8 / 18 page

M68AF511A

8/18

OPERATION

The M68AF511A has a Chip Enable power down

feature which invokes an automatic standby mode

whenever Chip Enable is de-asserted (E = High).

An Output Enable (G) signal provides a high

speed tri-state control, allowing fast read/write cy-

cles to be achieved with the common I/O data bus.

Operational modes are determined by device con-

trol inputs W and E as summarized in the Operat-

ing Modes table (Table 6).

Table 6. Operating Modes

Note: X = VIH or VIL.

Read Mode

The M68AF511A is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, and Chip Enable (E) is asserted. This pro-

vides access to data from eight of the 4,194,304

locations in the static memory array, specified by

the 19 address inputs. Valid data will be available

at the eight output pins within tAVQV after the last

stable address, providing G is Low and E is Low.

If Chip Enable or Output Enable access times are

not met, data access will be measured from the

limiting parameter (tELQV or tGLQV) rather than the

address. Data out may be indeterminate at tELQX

and tGLQX, but data lines will always be valid at

tAVQV.

Figure 7. Address Controlled, Read Mode AC Waveforms

Note: E = Low, G = Low, W = High.

Operation

DQ0-DQ7

Power

Output disabled

VIL

XVIH

Hi-Z

Active (ICC)

Read

VIL

VIH

VIL

Data Output

Active (ICC)

Write

VIL

Data Input

Active (ICC)

Deselect

VIH

Hi-Z

Standby (ISB)

AI03034

tAVAV

tAVQV

tAXQX

A0-A18

DQ0-DQ7

VALID

DATA VALID

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