 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
PC87365 데이터시트(PDF) 21 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87365 데이터시트(HTML) 21 Page - National Semiconductor (TI) |
|
|
21 / 215 page  1.0 Signal/Pin Connection and Description (Continued) 21 www.national.com 1.4 DETAILED SIGNAL/PIN DESCRIPTIONS This section describes all signals. Signals are organized in functional groups. 1.4.1 ACCESS.bus Interface (ACB) 1.4.2 Bus Interface 1.4.3 Clock 1.4.4 Fan Speed Control and Monitor (FSCM) Signal Pin(s) I/O Buffer Type Power Well Description SCL 54 I/O INSM/OD6 VDD ACCESS.bus Clock Signal. An internal pull-up is optional, depending upon the ACCESS.bus configuration register. SDA 55 I/O INSM/OD6 VDD ACCESS.bus Data Signal. An internal pull-up is optional, depending upon the ACCESS.bus configuration register. Signal Pin(s) I/O Buffer Type Power Well Description LAD0-3 15-18 I/O INPCI/OPCI VDD LPC Address-Data. Multiplexed command, address bi- directional data and cycle status. LCLK 11 I INPCI VDD LPC Clock. Practically, the PCI clock (up to 33 MHz). LDRQ 13 O OPCI VDD LPC DMA Request. Encoded DMA request for LPC I/F. LFRAME 14 I INPCI VDD LPC Frame. Low pulse indicates the beginning of new LPC cycle or termination of a broken cycle. LRESET 10 I INPCI VDD LPC Reset. Practically, the PCI system reset. PIRQ3-7 PIRQ9-12 PIRQ14-15 117-121 122-125 126-127 I INTS VDD Parallel Interrupt. Converts Parallel Port interrupts into Serial Interrupts by means of the Interrupt Serializer. SERIRQ 12 I/O INPCI/OPCI VDD Serial IRQ. The interrupt requests are serialized over a single pin, where each internal IRQ signal is delivered during a designated time slot. SMI 21 OD OD12 VDD System Management Interrupt. Signal Pin(s) I/O Buffer Type Power Well Description CLKIN 22 I INT VDD Clock In. 48 MHz clock input. Signal Pin(s) I/O Buffer Type Power Well Description FANIN0 FANIN1 FANIN2 4 2 128 I INTS VDD Fan Inputs. Used to feed the fan’s tachometer pulse to the Fan Speed Monitor. The rising edge indicates the completion of a half (or full) revolution of the fan. FANOUT0 FANOUT1 FANOUT2 5 3 1 O O2/14 VDD Fan Outputs. Pulse Width Modulation (PWM) signals, used to control the speed of cooling fans by controlling the voltage supplied to the fan’s motor. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
