Philips Semiconductors

Product data sheet

PCA9546

2004 Sep 30

8

Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits

is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an

extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an

acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock

pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of

the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

SW00368

DATA OUTPUT

BY RECEIVER

12

89

S

START condition

clock pulse for

acknowledgement

acknowledge

not acknowledge

S

SDA

0A

A

1

1

1

0

A2

A1

A0

SLAVE ADDRESS

start condition

R/W

acknowledge

from slave

acknowledge

from slave

B0

CONTROL REGISTER

X

P

SW00917

B1

XB2

XB3

X

Figure 10. WRITE control register

SDA

S1

A

NA

1

1

1

0

A2

A1

A0

start condition

R/W

acknowledge

from slave

CONTROL REGISTER

P

stop condition

last byte

SW00918

SLAVE ADDRESS

no acknowledge

from master

B0

XB1

X

B2

XB3

X

Figure 11. READ control register