PCM1730

SLES021 – NOVEMBER 2001

8

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functional description (continued)

Reset

Reset Removal

1024 System Clocks

VDD

2.4 V (Max)

2 V (Typ)

1.6 V (Min)

Internal Reset

System Clock

Figure 2. Power-On Reset Timing

Reset

Reset Removal

1024 System Clocks

Internal Reset

System Clock

RST (Pin 36)

50% of VDD

t(RST)

PARAMETER

MIN

UNIT

Reset pulse width low, t(RST)

20

ns

Figure 3. External Reset Timing

audio data interface

audio serial interface

The audio serial interface for the PCM1730 is comprised of a 3-wire synchronous serial port. It includes LRCK

(pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data

present on DATA into the audio interface’s serial shift register. Serial data is clocked into the PCM1730 on the

rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the serial

audio interface’s internal registers.

LRCK should be synchronous with the system clock. In the event these clocks are not synchronized, the

PCM1730 can compensate for the phase difference internally. If the phase difference between LRCK and SCKI

is greater than 6-bit clocks (BCK), the synchronization is performed internally. While the synchronization is

processing, the analog output is forced to bipolar zero level. The synchronization typically occurs in less than

one cycle of LRCK.

Ideally, it is recommended that LRCK and BCK be derived from the system clock input or output, SCKI or SCKO.