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QL8050 데이터시트(PDF) 35 Page - List of Unclassifed Manufacturers

부품명 QL8050
상세설명  LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
PDF  49 Pages
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QL8050 데이터시트(HTML) 35 Page - List of Unclassifed Manufacturers

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Preliminary

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The basic power equation which best models power consumption is given below:
P
TOTAL
= 0.350 + f[0.0031
η
LC +
0.0948
η
CKBF +
0.01
η
CLBF+
0.0263
η
CKLD+
0.543
η
RAM
+ 0.20
η
PLL+
0.0035
η
INP +
0.0257
η
OUTP]
(mW)
Where
•
η
LC is the total number of logic cells in the design
•
η
CKBF = # of clock buffers
•
η
CLBF = # of column clock buffers
•
η
CKLD = # of loads connected to the column clock buffers
•
η
RAM = # of RAM blocks
•
η
PLL = # of PLLs
•
η
INP is the number of input pins
•
η
OUTP is the number of output pins
NOTE:
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3RZHUXS6HTXHQFLQJ
)LJXUH  3RZHUXS 6HTXHQFLQJ
The following requirements must be met when powering up a device (refer to
)LJXUH ):
•
When ramping up the power supplies keep (VCCIO -VCC)MAX ≤ 500 mV. Deviation from this
recommendation can cause permanent damage to the device.
•
V
CCIO must lead VCC when ramping the device.
•
The power supply must be greater than or equal to 400 µs to reach V
CC. Ramping to
V
CC/VCCIO before reaching 400 µs can cause the device to behave improperly.
V
CCIO
V
CC
(V
CCIO -VCC)MAX
400 us
V
CC



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