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QL8250 데이터시트(PDF) 13 Page - List of Unclassifed Manufacturers

부품명 QL8250
상세설명  LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
PDF  49 Pages
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제조업체  ETC [List of Unclassifed Manufacturers]
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Logo ETC - List of Unclassifed Manufacturers

QL8250 데이터시트(HTML) 13 Page - List of Unclassifed Manufacturers

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Preliminary

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A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down
eliminates the need for external pull down resistors for used I/Os. The spec for pull-down current
is maximum of 150
µA under worst case condition.
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There are a maximum of eight global clock networks in each Eclipse-II device. Global clocks can
drive logic cells and I/O registers, ECUs, and RAM blocks in the device. All global clocks have
access to a Quad Net (local clock network) connection with a programmable connection to the
logic cell’s register clock input.
I/O Output Logic
PAD



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