REG102

2

SBVS024F

www.ti.com

PIN CONFIGURATIONS

Top View

V

OUT

(2)

V

OUT

(2)

GND

V

IN

(3)

V

IN

(3)

NC

Enable

SO-8

1

2

3

4

8

7

6

5

NOTES: (1) For REG102A-A: voltage setting resistor pin.

All other models: noise reduction capacitor pin.

(2) Both pin 1 and pin 2 must be connected.

(3) Both pin 7 and pin 8 must be connected.

SOT223-5

(U Package)

V

IN

GND

Enable

V

OUT

SOT23-5

1

2

3

5

4

(N Package)

(G Package)

Tab is GND

Enable

GND

V

IN

12

3

4

5

V

OUT

Output Short-Circuit Duration ...................................................... Indefinite

Lead Temperature (soldering, 3s) .................................................. +240

°C

NOTE: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper han-

dling and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PRODUCT

REG102xx-

yyyy/zzz

XX is package designator.

YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable).

ZZZ is package quantity.

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.

(2) Output voltages from 2.5V to 5.1V in 50mV increments are available; minimum order quantities apply. Contact factory for details and availability.