M38C37ECAFP datasheet(25/62 Pages) MITSUBISHI

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

38C3 Group

[Serial I/O Control Registers 1, 2 (SIOCON1,

SIOCON2)] 001916, 001A16

Each of the serial I/O control registers 1, 2 contains 8 bits that select

various control parameters of serial I/O.

qOperation in serial I/O mode

Either an internal clock or an external clock can be selected as the

synchronous clock for serial I/O transfer. A dedicated divider is built-

in as the internal clock, giving a choice of six clocks.

When internal clock is selected, serial I/O starts to transfer by a write

signal to the serial I/O register (address 001B16). After 8 bits have

been transferred, the SOUT pin goes to high impedance.

When external clock is selected, the clock must be controlled exter-

nally because the contents of the serial I/O register continue to shift

while the transfer clock is input. In this case, the SOUT pin does not

go to high impedance at the completion of data transfer.

The interrupt request bit is set at the end of the transfer of 8 bits,

regardless of whether the internal or external clock is selected.

Fig. 23 Structure of serial I/O control register

Fig. 24 Serial I/O timing (for LSB first)

Serial I/O control register 1

(SIOCON1 : address 001916)

Internal synchronous clock selection bits

b2 b1 b0

0 0 0 : f(XIN)/8 or f(XCIN)/8

0 0 1 : f(XIN)/16 or f(XCIN)/16

0 1 0 : f(XIN)32 or f(XCIN)/32

0 1 1 : f(XIN)/64 or f(XCIN)/64

1 1 0 : f(XIN)/128 or f(XCIN)/128

1 1 1 : f(XIN)/256 or f(XCIN)/256

Serial I/O port selection bit (P40, P45, P46)

0 : I/O port

1 : SOUT, SCLK1, SCLK2 signal pin

SRDY output selection bit (P47)

0 : I/O port

1 : SRDY signal pin

Transfer direction selection bit

0 : LSB first

1 : MSB first

Synchronous clock selection bit

0 : External clock

1 : Internal clock

P-channel output disable bit (P40, P45, P46)

0 : CMOS output (in output mode)

1 : N-channel open-drain (in output mode)

Serial I/O control register 2

(SIOCON2: address 001A16)

Synchronous clock output pin selection bit

0 : SCLK1

1 : SCLK2

Not used (returns “0” when read)

Interrupt request bit set

Synchronous clock

Transfer clock

Serial I/O register

write signal

Serial I/O output

SOUT

Serial I/O input

SIN

Receive enable signal

SRDY

Note: When internal clock is selected, the SOUT pin goes to high impedance after

transfer ends.

(Note)

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