ST16C580

16

Rev. 1.20

REGISTER FUNCTIONAL DESCRIPTIONS

The following table delineates the assigned bit functions for the fifteen 580 internal registers. The assigned

bit functions are more fully defined in the following paragraphs.

Table 5, ST16C580 INTERNAL REGISTERS

A2 A1 A0

Register

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

[Default]

Note *5

General Register Set

0

0

0

RHR [XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

0

0

0

THR [XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

0

0

1

IER [00]

CTS

RTS

Xoff

Sleep

modem

receive

transmit

receive

interrupt

interrupt

interrupt

mode

status

line

holding

holding

interrupt

status

register

register

interrupt

0

1

0

FCR [00]

RCVR

RCVR

TX

TX

DMA

XMIT

RCVR

FIFO

trigger

trigger

trigger

trigger

mode

FIFO

FIFO

enable

(MSB)

(LSB)

(MSB)

(LSB)

select

reset

reset

0

1

0

ISR [01]

FIFO’s

FIFO’s

INT

INT

INT

INT

INT

INT

enabled

enabled

priority

priority

priority

priority

priority

status

bit-4

bit-3

bit-2

bit-1

bit-0

0

1

1

LCR [00]

divisor

set

set

even

parity

stop

word

word

latch

break

parity

parity

enable

bits

length

length

enable

bit-1

bit-0

1

0

0

MCR [00]

Clock

IR

0

loop

-OP2

-OP1

-RTS

-DTR

select

enable

back

1

0

1

LSR [60]

FIFO

trans.

trans.

break

framing

parity

overrun

receive

data

empty

holding

interrupt

error

error

error

data

error

empty

ready

1

1

0

MSR [X0]

CD

RI

DSR

CTS

delta

delta

delta

delta

-CD

-RI

-DSR

-CTS

1

1

1

SPR [FF]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

Special Register Set: Note *3

0

0

0

DLL [XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

0

0

1

DLM [XX]

bit-15

bit-14

bit-13

bit-12

bit-11

bit-10

bit-9

bit-8