VIA Technologies, Inc.

VT8225

-2-

VT8225 Signal Description

Symbol Pin No.

Type

Functions

X1

X2

2

3

I

I/O

These pins form an on-chip reference oscillator when connected to

terminals of an external parallel resonant crystal (norminally

14.318Mhz). X1 may also serve as input for an externally

generated reference signal.

S0

S1

S2

S3

4

5

10

9

I

I

I

I

Frequency select inputs. These inputs control the MCLK frequency

selection. All these inputs have internal pull-ups. Table 1 below

shows the output frequency selection conditions.

MCLK

8

O

Master clock output. Programmable output frequencies can

be selected using So-S3.

RESET#

11

O

Chip reset, negative true.

TS

1

I

Tri-state input pin. When high, all outputs are tri-stated. When low

outputs are enabled. This pin has an internal pull-down.

OSC

13

O

14.31818 Mhz output. Buffered output of on-chip reference

oscillaor or externally provided reference.

PD

6

O

This is the phase detector output for the clock generator. It is

single-ended, tri-state output for use as loop error signal. A 0.1uF

capacitor to ground should be connected from this pin to form the

loop filter.

VSS

7

Ground

Digital Negative power supply.

AVSS

12

Ground

Analog Negative power supply.

VDD

14

Power

Positive power supply.

MCLK FREQUENCY SELECTION

INPUTS

MCLK OUTPUT

S2

S1

S0

S3=1 (Bank 1)

S3=0 (Bank 0)

0

0

0

8 Mhz

16 Mhz

0

0

1

20 Mhz

40 Mhz

0

1

0

25 Mhz

50 Mhz

0

1

1

40 Mhz

80 Mhz

1

0

0

33.3 Mhz

66.6 Mhz

1

0

1

50 Mhz

100 Mhz

1

1

0

4 Mhz

8 Mhz

1

1

1

2 Mhz

4 Mhz

Table 1 clock frequency selection

Note : The smooth transition of frequency change is only allowed within the same selection bank.