AD15700SLASHPCB datasheet(7/44 Pages) AD

7 / 44 page

REV. A

AD15700

–7–

14-BIT DAC TIMING CHARACTERISTICS1, 2

(VDD = 5 V,

5%, VREF = 2.5 V, AGND = DGND = 0 V. All Specifications

TA = TMIN to TMAX, unless otherwise noted).

Parameter

Limit at TMIN, TMAX All Versions

Unit

Description

fSCLK

MHz max

SCLK Cycle Frequency

ns min

SCLK Cycle Time

ns min

SCLK High Time

ns min

SCLK Low Time

ns min

CS_DAC Low to SCLK High Setup

ns min

CS_DAC High to SCLK High Setup

ns min

SCLK High to

CS_DAC Low Hold Time

ns min

SCLK High to

CS_DAC High Hold Time

ns min

Data Setup Time

ns min

Data Hold Time

t10

ns min

CS_DAC High Time between Active Periods

NOTES

1Guaranteed by design. Not production tested.

2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90%

of 3 V and timed from a voltage level of 1.6 V).

Specifications subject to change without notice.

DB13

DB0

DIN

CS_DAC

SCLK

Figure 3. Timing Diagram

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