AFE1302

7

SBWS014

CLIP EVENT

Receive data (AFEG_RX) is generated in the AFE1302 with

additional headroom. For the one sign-bit case, if AFEG_RX

data is greater than 7FFF, it will be clipped to 7FFF.

If AFEG_RX data is less than 8000, it will be clipped to

8000. For the two sign-bit case, if AFEG_RX data is greater

than 3FFF, it will be clipped to 3FFF. If AFEG_RX data is

less than C000, it will be clipped to C000. During clip, pin

CLIP will be asserted HIGH for monitoring purposes. Pin

CLIP will remain HIGH until 0 is written to address = 010,

bit 3 in AFE1302 control register.

FIGURE 3. AFE1302 Program Timing.

CLWD

CTRLIN

CLWD

CTRLIN

Start Bit

12 Data Bits

≥ 16 HIGH Stop Bits

Data ID

3 Bit

t

S

t

H

NOTE: CLWD = 8.832MHz/N; t

PROGRAMMING THE AFE1302

The internal AFE control register, as shown in Table V, is

used to set the programmable features of the AFE1302 and to

set the VCXO frequency. Serial data is sent from the DSP to

the AFE control register on the CTRLIN pin in 16-bit blocks.

This data is clocked into the AFE1302 on the falling edge of

CLWD. AFEREG data is valid when followed by at least 16

stop bits (HIGH). The timing is shown in Figure 3. During

programming, all AFE1302 functions are active. Data ID

code 0 through 5 must be configured for normal operation;

data ID code 6 and 7 are reserved for future use.