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CLC5903 데이터시트(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 CLC5903
상세설명  Dual Digital Tuner / AGC
PDF  29 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

CLC5903 데이터시트(HTML) 4 Page - National Semiconductor (TI)

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4
tMRSU
MR Setup Time to CKA|B (Figure 5)
6
ns
tMRH
MR Hold Time to CKA|B (Figure 5)
2
ns
tSISU
SI Setup Time to CKA|B (Figure 6)
6
ns
tSIH
SI Hold Time from CKA|B (Figure 6)
2
ns
tSIW
SI Pulse Width (Figure 6)
4
CK periods
tCKDC
CKA|B duty cycle (Figure 7)
40
60
%
tRF
CKA|B rise and fall times (VIL to VIH) (Figure 7)
2ns
tSU
Input setup before CKA|B goes high (A|BIN) (Figure 7)
3
ns
tHD
Input hold time after CKA|B goes high (A|BIN) (Figure 7)
1
ns
tCKL
Minimum time low for CK = CKA | CKB (Figure 8)
3.1
ns
tSTIW
A|BSTROBE Inactive Pulse Width (Figure 9)
2
CK period
tGSTB
A|BGAIN setup before A|BSTROBE (Figure 9)
6
ns
tSFSV
SCK to SFS Valid (Note 3) (Figure 10)
-1
5
ns
tOV
SCK to A|BOUT Valid (Note 4) (Figure 10)
-1
5
ns
tRDYW
RDY Pulse Width (Figure 10)
2
CK periods
tRDYV
SCK to RDY valid (Figure 10)
-1
5
ns
tOENV
POUT_EN Active to POUT[15..0] Valid (Figure 11)
12
ns
tOENT
POUT_EN Inactive to POUT[15..0] Tri-State (Figure 11)
10
ns
tSELV
PSEL[2..0] to POUT[15..0] Valid (Figure 12)
13
ns
tPOV
RDY to POUT[15..0] New Value Valid (Note 5) (Figure 13)
7
ns
tJPCO
Propagation Delay TCK to TDO (Figure 14)
25
ns
tJSCO
Propagation Delay TCK to Data Out (Figure 14)
35
ns
tJPDZ
Disable Time TCK to TDO (Figure 14)
25
ns
tJSDZ
Disable Time TCK to Data Out (Figure 14)
35
ns
tJPEN
Enable Time TCK to TDO (Figure 14)
0
25
ns
tJSEN
Enable Time TCK to Data Out (Figure 14)
0
35
ns
tJSSU
Setup Time Data to TCK (Figure 14)
10
ns
tJPSU
Setup Time TDI, TMS to TCK (Figure 14)
10
ns
tJSH
Hold Time Data to TCK (Figure 14)
45
ns
tJPH
Hold Time TCK to TDI, TMS (Figure 14)
45
ns
tJCH
TCK Pulse Width High (Figure 14)
50
ns
tJCL
TCK Pulse Width Low (Figure 14)
40
ns
JTAGFMAX
TCK Maximum Frequency (Figure 14)
10
MHz
tCSU
Control Setup before the controlling signal goes low (Figure 15)
5
ns
tCHD
Control hold after the controlling signal goes high (Figure 15)
5
ns
AC Characteristics (Continued)
(FS=78MHz, CIC Decimation=48, F2 Decimation=2; unless specified)
Symbol
Parameter (CL=50pF)
Min
Typ
Max
Units



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