REF62xx

AGND

REFP

REFM

ADC

AGND

EN

Copyright © 2016, Texas Instruments Incorporated

28

REF6225, REF6230, REF6233, REF6241, REF6245, REF6250

SBOS748 – SEPTEMBER 2016

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Product Folder Links: REF6225 REF6230 REF6233 REF6241 REF6245 REF6250

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Copyright © 2016, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

Figure 61 illustrates an example of a PCB layout for a data-acquisition system using the REF62xx. Some key

considerations are:

•

Connect low-ESR, 0.1-μF ceramic bypass capacitors between the VIN pin and ground.

•

•

Run two separate traces between VOUT_F, VOUT_S and the output capacitor, as shown in Figure 61.

•

Short the GND_F and GND_S pins with a solid plane, and extend this plane to connect to the output

•

Use a solid ground plane to help distribute heat and reduces electromagnetic interference (EMI) noise pickup.

•

Place the external components as close to the device as possible. This configuration prevents parasitic errors

(such as the Seebeck effect) from occurring.

•

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when absolutely necessary.

11.2 Layout Example

Figure 61. Layout Example