DS1830U datasheet(4/7 Pages) DALLAS

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DS1830U 데이터시트(PDF) 4 Page - Dallas Semiconductor

부품명	DS1830U

상세설명	Reset Sequence Pushbutton

PDF	7 Pages

Scroll/Zoom	100%

제조업체	DALLAS [Dallas Semiconductor]

홈페이지	https://www.maximintegrated.com/en.html

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4 / 7 page

D1830/A

4 of 7

APPLICATION DIAGRAM — CASCADE DELAY CONFIGURATIONS Figure 4

Note 1: The RST3 output tied to the pushbutton reset would be pulled to VCC through the 40kW resistor in

the pushbutton input. If a stronger pull-up is required an additional pull-up resistor could be added.

Note 2: When using the cascade configuration, it is important that the TOL pins of the master and the

slave are configured so that the master’s VCCTP is greater than the slave’s VCCTP. This will ensure that

when the master’s higher VCCTP is crossed, the resets will ripple through to the slave.

TIMING DIAGRAM — POWER-DOWN Figure 5

MASTER

SLAVE

SEE NOTE 2

SEE NOTE 1

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