ICS8624 datasheet(6/16 Pages) ICST

6 / 16 page

8624BY

www.icst.com/products/hiperclocks.html

REV. C JUNE 15, 2004

Integrated

Circuit

Systems, Inc.

ICS8624

LOW SKEW, 1-TO-5

DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

PARAMETER MEASUREMENT INFORMATION

CYCLE-TO-CYCLE JITTER

PHASE JITTER AND STATIC PHASE OFFSET

OUTPUT RISE/FALL TIME

Clock

Outputs

20%

80%

20%

t F

VOD

tsk(o)

nQx

nQy

DIFFERENTIAL INPUT LEVEL

OUTPUT SKEW

3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

HSTL

nQx

CMR

Cross Points

GND

CLK0,

CLK1

nCLK0,

nCLK1

nQx

nCLK0,

nCLK1

CLK0,

CLK1

nQ0:nQ4

Q0:Q4

VDD,

VDDA

3.3V±5% or 10%

VDDO

1.8V±0.2V

OUTPUT PULSE WIDTH/PERIOD

nQ0:nQ4

Q0:Q4

PROPAGATION DELAY

➤

tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

tcycle n

tcycle n+1

(where

t(Ø) is any random sample, and t(Ø) mean is the average

of the sampled cycles measured on controlled edges)

t(Ø) mean = Static Phase Offset

➤t(Ø)

nCLK0,

nCLK1

nFB_IN

FB_IN

tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter

CLK0,

CLK1

Pulse Width

t PERIOD

DDO

GND

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