AR0230CS datasheet(9/33 Pages) ONSEMI

9 / 33 page

AR0230CS/D Rev. 9, 6/16 EN

©Semiconductor Components Industries, LLC,2016.

AR0230CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

Functional Overview

Table 3:

Pin Descriptions, 80-ball iBGA

Name

iBGA Pin

Type

Description

SLVS0_P

Output HiSPi serial data, lane 0, differential P.

SLVS1_P

Output HiSPi serial data, lane 1, differential P.

SLVSC_P

Output HiSPi serial DDR clock differential P.

SLVS2_P

Output HiSPi serial data, lane 2, differential P.

SLVS3_P

Output HiSPi serial data, lane 3, differential P.

VDD_PLL

Power

PLL power.

SLVS0_N

Output HiSPi serial data, lane 0, differential N.

SLVS1_N

Output HiSPi serial data, lane 1, differential N.

SLVSC_N

Output HiSPi serial DDR clock differential N.

SLVS2_N

Output HiSPi serial data, lane 2, differential N.

SLVS3_N

Output HiSPi serial data, lane 3, differential N.

SHUTTER

Output Control for external mechanical shutter. Can be left floating if not used.

VAA

C1, G1, D9, F9

Power

Analog power.

AGND

C2, G2, D8, E8, F8

Power

Analog ground.

VDD_SLVS

Power

0.3V-0.6V or 1.7V - 1.9V port to HiSPi Output Driver. Set the High_VCM

(R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 – 1.9V.

VDD

C5, J5, A9, H9, A7, D1, F1

Power

Digital power.

Reserved

C9, F7

DGND

B7, C7, D7, E7, G7, B8, C8, G8,

D2, E2, F2, H2, C3, G3, H3, C6,

Power

Digital ground.

EXTCLK

Input

External input clock.

PIXCLK

Output Pixel clock out. Dout is valid on rising edge of this clock.

SADDR

Input

Two-Wire Serial address select. 0: 0x20. 1: 0x30

TRIGGER

Input

Exposure synchronization input.

VAA_PIX

Power

Pixel power.

VDD_IO

E1, H1, J2, J7, A8, G9, J9

Power

I/O supply power.

SDATA

I/O

Two-Wire Serial data I/O.

FLASH

Output Flash control output.

FRAME_VALID

Output Asserted when Dout frame data is valid.

SCLK

Input

Two-Wire Serial clock input.

DOUT11

Output Parallel pixel data output (MSB)

DOUT10