LPC2292 datasheet(13/40 Pages) PHILIPS

13 / 40 page

Philips Semiconductors

LPC2292/LPC2294

16/32-bit ARM microcontrollers with external memory interface

Preliminary data

Rev. 01 — 05 February 2004

13 of 40

9397 750 12748

Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is

assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the

ARM processor. The fastest possible FIQ latency is achieved when only one request

is classiﬁed as FIQ, because then the FIQ service routine can simply start dealing

with that device. But if more than one request is assigned to the FIQ class, the FIQ

service routine can read a word from the VIC that identiﬁes which FIQ source(s) is

(are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be

assigned to this category. Any of the interrupt requests can be assigned to any of the

16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the

lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to

produce the IRQ signal to the ARM processor. The IRQ service routine can start by

reading a register from the VIC and jumping there. If any of the vectored IRQs are

requesting, the VIC provides the address of the highest-priority requesting IRQs

service routine, otherwise it provides the address of a default routine that is shared by

all the non-vectored IRQs. The default routine can read another VIC register to see

what IRQs are active.

6.5.1

Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device

has one interrupt line connected to the Vectored Interrupt Controller, but may have

several internal interrupt ﬂags. Individual interrupt ﬂags may also represent more than

one interrupt source.

Table 4:

Interrupt sources

Block

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

Reserved for software interrupts only

ARM Core

Embedded ICE, DbgCommRx

ARM Core

Embedded ICE, DbgCommTx

Timer0

Match 0 - 3 (MR0, MR1, MR2, MR3)

Capture 0 - 3 (CR0, CR1, CR2, CR3)

Timer1

Match 0 - 3 (MR0, MR1, MR2, MR3)

Capture 0 - 3 (CR0, CR1, CR2, CR3)

UART0

Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

UART1

Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

PWM0

Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

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