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TLS810B1 데이터시트(PDF) 5 Page - Infineon Technologies AG |
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TLS810B1 데이터시트(HTML) 5 Page - Infineon Technologies AG |
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5 / 24 page ![]() Data Sheet 5 Rev. 1.0 2015-11-02 TLS810B1LDV50 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment in PG-TSON-10 Package Figure 3 Pin Configuration TLS810B1 in PG-TSON-10 package 3.2 Pin Definitions and Functions in PG-TSON-10 Package Pin Symbol Function 1I Input It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close to the IC terminals, in order to compensate line influences. 2N.C. Not connected 3EN Enable Integrated pull-down resistor. Enable the IC with high level input signal. Disable the IC with low level input signal. 4N.C. Not connected 5GND Ground 6N.C. Not connected 7N.C. Not connected 8N.C. Not connected 9Q Output Connect an output capacitor CQ to GND close to the IC’s terminals, respecting the values specified for its capacitance and ESR in Table 2 “Functional Range” on Page 8. I N.C. N.C. EN GND N.C. N.C. 1 2 3 TSON-10 5 10 9 8 7 6 N.C. Q N.C. 4 |
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