AS4C2M32SA datasheet(11/54 Pages) ALSC

11 / 54 page

Figure 11. Write Interrupted by a Write (Burst Length = 4)

CLK

COMMAND

NOP

WRITE A WRITE B

NOP

DIN A0

DIN B0

DIN B1

DIN B2

DIN B3

The Read command that interrupts a write burst without auto precharge function should be issued one

cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention,

input data must be removed from the DQs at least one clock cycle before the first read data appears on

the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be

ignored and writes will not be executed.

Figure 12. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)

Don’t Care

CLK

COMMAND

CAS# latency=2

tCK2, DQ

CAS# latency=3

tCK3, DQ

Input data must be removed from the DQ at least one clock cycle before

the Read data appears on the outputs to avoid data contention

NOP

WRITE A

READ B

NOP

DIN A0

DOUT B0 DOUT B1 DOUT B2 DOUT B3

DOUT B3

DOUT B2

DOUT B1

DOUT B0

DIN A0

The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge

function should be issued m cycles after the clock edge in which the last data-in element is registered,

where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be

used to mask input data, starting with the clock edge following the last data-in element and ending with

the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following

figure).

AS4C2M32SA-6TIN

AS4C2M32SA-6TCN

AS4C2M32SA-7TCN

Confidential

-11/54-

Rev.1.0 Sep. 2015

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