TUSB9261-Q1

SLLSEE2A – JANUARY 2014 – REVISED JANUARY 2014

www.ti.com

Table 1. I/O Definitions

I/O TYPE

DESCRIPTION

I

Input

O

Output

I/O

Input - Output

PU

Internal pull-up resistor

PD

Internal pull-down resistor

PWR

Power signal

Table 2. Clock and Reset Signals

TERMINAL

I/O

DESCRIPTION

PIN

NAME

NO.

I

Global power reset. This reset brings all of the TUSB9261-Q1 internal registers to their default

GRSTz

4

PU

states. When GRSTz is asserted, the device is completely nonfunctional.

Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately

XI

52

I

be driven by the output of an external oscillator. When using a crystal a 1-M

Ω feedback resistor

is required between X1 and XO.

Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an

XO

54

O

external oscillator this pin may be left unconnected. When using a crystal a 1-M

Ω feedback

resistor is required between X1 and XO.

Frequency select. These terminals indicate the oscillator input frequency and are used to

configure the correct PLL multiplier. The field encoding is as follows:

FREQSEL[1]

FREQSEL[0]

INPUT CLOCK FREQUENCY

I

0

0

20 MHz

FREQSEL[1:0]

31, 30

PU

0

1

25 MHz

1

0

30 MHz

1

1

40 MHz

TERMINAL

I/O

DESCRIPTION

PIN

NAME

NO.

SATA_TXP

57

O

Serial ATA transmitter differential pair (positive)

SATA_TXM

56

O

Serial ATA transmitter differential pair (negative)

SATA_RXP

60

I

Serial ATA receiver differential pair (positive)

SATA_RXM

59

I

Serial ATA receiver differential pair (negative)

(1)

Note that the default firmware and reference design for the TUSB9261-Q1 have the SATA TXP/TXM swapped for ease of routing in the

reference design. If you plan to use the TI default firmware please review the reference design in the TUSB9261 DEMO User’s Guide

(SLLU139) for proper SATA connection.

4

Submit Documentation Feedback

Copyright © 2014, Texas Instruments Incorporated

Product Folder Links :TUSB9261-Q1