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ST92185B 데이터시트(PDF) 138 Page - STMicroelectronics |
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ST92185B 데이터시트(HTML) 138 Page - STMicroelectronics |
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138 / 178 page ![]() 138/178 ST92185B - SYNC CONTROLLER SYNC CONTROLLER (Cont’d) 7.5.4.2 Composite Sync Input Mode This mode is very similar to the “Standard Sync In- put Mode” described above. It is also accessed when both MOD1 and MOD0 bits are reset. In Composite Sync mode, a single CSYNC/ HSYNC input pin is used to enter both the horizon- tal and vertical sync pulses (VSEP control bit is set to 1). In this mode, the VSYNC pin must be tied to VSS on the application board to prevent a floating CMOS input configuration. The CSYNC signal characteristics are assumed to perfectly respect the STV2160 TXTOUT pin spec- ification which is reviewed in Figure 84 & Figure 85. The vertical sync signal is extracted from the CSYNC signal by the mean of an Up/Down coun- ter used as a digital integrator. The counter works in “Up” mode during the sync pulses. Two time constants can be programmed using the VDLY control bit (refer to the register description). The smallest one corresponds to 16µs; the second one being 32µs. Figure 84. STV2160 TXTOUT Timings n 1st TV Field 2nd TV Field TXTOUT TXTOUT 623 624 625 12 34 5 6 311 312 313 314 315 316 317 318 319 8µs 8µs 58µs 38µs 8µs 8µs 8µs 58µs 6µs 8µs VR02092B |
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