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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST92185B3T1 데이터시트(PDF) 31 Page - STMicroelectronics |
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ST92185B3T1 데이터시트(HTML) 31 Page - STMicroelectronics |
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31 / 178 page  31/178 ST92185B - DEVICE ARCHITECTURE Bits 4:2 = PRS[2:0]: CPUCLK Prescaler. These bits load the prescaler division factor for the internal clock (INTCLK). The prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. Refer to the Reset and Clock Control chapter for further information. Bit 1 = BRQEN: Bus Request Enable. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on BREQ pin (where available). Note: Disregard this bit if BREQ pin is not availa- ble. Bit 0 = HIMP: High Impedance Enable. When any of Ports 0, 1, 2 or 6 depending on de- vice configuration, are programmed as Address and Data lines to interface external Memory, these lines and the Memory interface control lines (AS, DS, R/W) can be forced into the High Impedance |
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