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TAS5026 데이터시트(PDF) 39 Page - Texas Instruments

부품명 TAS5026
상세설명  SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR
PDF  48 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

TAS5026 데이터시트(HTML) 39 Page - Texas Instruments

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Specifications
34
SLES041B—November 2002
TAS5026
5.4.2 Serial Audio Port
5.4.2.1
Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
Frequency, SCLK
12.288
MHz
tsu(SDIN)
SDIN setup time before SCLK rising edge
20
ns
th(SDIN)
SDIN hold time before SCLK rising edge
10
ns
f(LRCLK)
LRCLK frequency
32
48
192
kHz
MCLK_IN duty cycle
50%
SCLK duty cycle
50%
LRCLK duty cycle
50%
tsu(LRCLK)
LRCLK setup time before SCLK rising edge
20
ns
MCLK High and Low time
20
ns
5.4.2.2
Serial Audio Ports Master Mode, Load Conditions 50 pF Over Recommended
Operating Conditions (Unless Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
t(MSD)
MCLK_IN to SCLK
0
5
ns
t(MLRD)
MCLK_IN to LRCLK
0
5
ns
5.4.2.3
DSP Serial Interface Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
SCLK frequency
12.288
MHz
td(FS)
Delay time, SCLK rising to Fs
ns
tw(FSHIGH)
Pulse duration, sync
1/(64xfs)
ns
tsu(SDIN)
SDIN and LRCLK setup time before SCLK falling edge
20
ns
th(SDIN)
SDIN and LRCLK hold time from SCLK falling edge
10
ns
SCLK duty cycle
50%
th(SDIN)
tsu(SDIN)
SCLK
SDIN
Figure 5–6. Right-Justified, IIS, Left-Justified Serial Protocol Timing



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