ML7033 datasheet(21/52 Pages) LAPIS

21 / 52 page

FEDL7033-04

ML7033

21/52

Table 4

State of PCMOUT in 14-bit Linear PCM Mode with LIN (CR0-B3) bit = “1”

PDN pin

MODE1 bit

MODE0 bit

ALAW bit

CH2 PCM Data

CH1 PCM Data

0/1

Hi-Z *1

ALL “0”

Operate

ALL “0”

0/1

Operate

Table 5

State of Analog Output Pins

PDN

MODE1

bit

MODE0

bit

GSX1

GSX2

AOUT1

AOUT2

SGC

MCU

Interface

0/1

Hi-Z

AG level *2

Operate

Hi-Z

AG level *2

Operate

Hi-Z

Operate

Hi-Z

Operate

Hi-Z

Operate

Hi-Z

Operate

The data will be ‘H’ by an external pull-up resistor.

Output impedance = about 50 k



F2_1, F1_1, F0_1, F2_2, F1_2, F0_2

The F2_n, F1_n and F0_n pins are data outputs used when the SLIC connected to the corresponding channel is

an Intersil RSLIC

TM series device. The output levels from the F2_n, the F1_n and F0_n pins are determined by

the F2_n, F1_n, and F0_n register bits (CR6-B7 to B5 and CR13-B7 to B5). By inputting these outputs directly

into the corresponding input pin of the SLIC device, the SLIC operating mode selection is possible.

Even in the power-down state with the

PDN pin is asserted, these pins remain functional.

E0_1, E0_2

The E0_n pins are the detector mode selection data outputs. These pins are used when the SLIC connected to the

corresponding channel is an Intersil RSLIC

TM series device. Though the output level from the E0_n pin is

determined by the E0_n bit (CR6-B2/CR13-B2), the output level changes in 20

s (= hold timer) in the

power-on mode with the

PDN pin = logic “1” and in 200 ns in the power-down mode with the PDN pin = logic

“0” after the change of E0_n bit (CR6-B2 /CR13-B2). Refer to Figure 6 for information.

What event is actually detected by the SLIC is determined by the combination of the F2_n, F1_n, F0_n and E0_n

pins. Refer to Table 6 for more information. By connecting the output directly into the corresponding input pin

of the SLIC device, detector mode selection in the SLIC is possible. Even in the power-down state with the

PDN

pin = logic “0”, this pin remains functional. However, the hold timer is ignored in this state.

ML7033 데이터시트(PDF) 21 Page - LAPIS Semiconductor Co., Ltd.

ML7033 데이터시트(HTML) 21 Page - LAPIS Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

데이터시트 다운로드

링크 URL