DM9301F datasheet(8/22 Pages) ETC

8 / 22 page

DM9301

100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter

Final

Version: DM9301-DS-F02

May 8, 2000

Diagnostic Port Interface (Continued)

39, 40

MUXCTL1,

MUXCTL0

Mux. Control 1 and 0:

Used for testing the DM9301 Data Paths. Set to zero for

normal operation.

Initiated at a H/W reset. Active high.

MUXCTL1 MUXCTL0

DATA PATH

Normal, FX to TX and TX to FX

TX Transmit from TXD[4:0]

TXCLK from TX PLL

TX Receive to RXD[4:0]

RXCLK from TX receive clock

FX Transmit from TXD[4:0]

TXCLK from FX PLL

FX Receive to RXD[4:0]

RXCLK from FX receive clock

TX Transmit from TXD[4:0]

TXCLK from TX PLL

FX Receive to RXD[4:0]

RXCLK from FX receive clock

65, 54,

55, 57,

58, 60,

TPO6, TPO5,

TPO4, TPO3,

TPO2, TPO1,

TPO0

Test Port Output:

Reflects the DM9301 internal status. Selection of status

indicators is made by using TPEN and TPMUX.

Initiated at a H/W reset. Active high.

92, 91, 89,

TPI3, TPI2, TPI1,

TPI0,

Test Port Input:

Controls the DM9301 internal test features. Selection of

input control is made by using TPEN and TPMUX.

TPEN must be true (one) for this signal to take effect.

Initiated at a H/W reset. Active high.

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