P89LPC930FDH datasheet(7/55 Pages) PHILIPS

7 / 55 page

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 — 15 December 2004

7 of 55

9397 750 14472

P1.0 - P1.7

18, 17, 12,

11, 10, 6,

5, 4

I/O, I [1]

Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type, except for

three pins as noted below. During reset Port 1 latches are conﬁgured in the input only

mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins

as inputs and outputs depends upon the port conﬁguration selected. Each of the

conﬁgurable port pins are programmed independently. Refer to Section 8.11.1 “Port

conﬁgurations” and Table 7 “DC electrical characteristics” for details. P1.2 - P1.3 are

open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

I/O

P1.0 — Port 1 bit 0.

TxD — Transmitter output for the serial port.

I/O

P1.1 — Port 1 bit 1.

RXD — Receiver input for the serial port.

I/O

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow output (open-drain when used

as output).

I/O

SCL — I2C serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

I/O

SDA — I2C serial data input/output.

P1.4 — Port 1 bit 4.

INT1 — External interrupt 1 input.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during Power-on or if selected via UCFG1. When

functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O

ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force In-System

Programming mode. When using an oscillator frequency above 12 MHz, the

reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until VDD has reached its speciﬁed level.

When system power is removed VDD will fall below the minimum speciﬁed

operating voltage. When using an oscillator frequency above 12 MHz, in some

applications, an external brownout detect circuit may be required to hold the

device in reset when VDD falls below the minimum speciﬁed operating voltage.

I/O

P1.6 — Port 1 bit 6.

I/O

P1.7 — Port 1 bit 7.

Table 3:

Pin description…continued

Symbol

Type

Description

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