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DS20005612A-page 7

DSC400

4.2

LVDS

FIGURE 4-2:

Typical LVDS Termination Scheme.

If the 100Ω clamping resistor does not exist inside the receiving device, it should be added externally on the PCB and

placed as close as possible to the receiver.

Note 1:

See the Output Waveform section for more information.

2:

TABLE 4-2:

LVDS OUTPUTS

Parameter

Symbol

Min.

Typ.

Max.

Units

Condition

Output Offset

Voltage

1.125

—

1.4

V

R = 100Ω Differential

Delta Offset

Voltage

——

50

mV

—

Peak-to-Peak

Output Swing

—

350

—

mV

Single-Ended

Output

Transition Time

(Note 1)

—

200

—

ps

—

200

—

Frequency

2.3

—

460

MHz

Single Frequency

Output Duty

Cycle

SYM

48

—

52

%

Differential

IO Supply

Current (Note 2)

—

9

12

mA

Per Output at 125 MHz.

Period Jitter

—2.5

—

Integrated

Phase Noise

—0.28—

—

0.4

—

100 kHz to 20 MHz @ 156.25 MHz

—

1.7

2.0

12 kHz to 20 MHz @156.25 MHz

100 Ω

100 Ω

Load (receiver IC)