VOLUME CONTROL

The internal Stereo Volume Control is set by changing bits 7 through 11 in the SPI interface, as shown in table 3 below. The zero

dB setting is for 3V VDD operation and the +3dB is for 5V VDD.

Table 3. Volume Control Settings

Gain (dB)

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

HP_L & HP_R

-43.5

0

0

0

0

0

-42.0

0

0

0

0

1

-40.5

0

0

0

1

0

-39.0

0

0

0

1

1

-37.5

0

0

1

0

0

-36.0

0

0

1

0

1

-34.5

0

0

1

1

0

-33.0

0

0

1

1

1

-31.5

0

1

0

0

0

-30.0

0

1

0

0

1

-28.5

0

1

0

1

0

-27.0

0

1

0

1

1

-25.5

0

1

1

0

0

-24.0

0

1

1

0

1

-22.5

0

1

1

1

0

-21.0

0

1

1

1

1

-19.5

1

0

0

0

0

-18.0

1

0

0

0

1

-16.5

1

0

0

1

0

-15.0

1

0

0

1

1

-13.5

1

0

1

0

0

-12.0

1

0

1

0

1

-10.5

1

0

1

1

0

-9.0

1

0

1

1

1

-7.5

1

1

0

0

0

-6.0

1

1

0

0

1

-4.5

1

1

0

1

0

-3.0

1

1

0

1

1

-1.5

1

1

1

0

0

0.0

1

1

1

0

1

1.5

1

1

1

1

0

3.0

1

1

1

1

1

BYPASS CHARGE RATE BIT 12

This control pin allows the user to change the Bypass Ca-

pacitor’s charge rate by a factor of two. Setting this bit at

zero will set the circuit to it’s normal 1x rate. Setting the bit to

High will double the charge rate and allow the part to turn on

faster with a slight degradation in turn on click/pop noise.

BITS 5, 13,14, and 15

Bits 13, 14, and 15 are all reserve bits and must be set to

low/zero/ground.

Bit 5 must be set High.

SPI CONTROL INTERFACE BUS (J1)

SPI DATA: This is the serial data pin.

SPI CLK: This is the clock input pin.

SPI ENABLE: This is the SPI enable pin.

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