LPC47N267 datasheet(32/180 Pages) SMSC

32 / 180 page

SMSC DS – LPC47N267

Page 32

Rev. 10/23/2000

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value

programmed in the Force FDD Status Change Register (CR17).

see the Configuration section for register

description.

PS/2 Mode

DSK

CHG

DRATE

SEL1

DRATE

SEL0

nHIGH

nDENS

RESET

COND.

N/A

BIT 0 nHIGH DENS

This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are

selected.

BITS 1 - 2 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data

rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BITS 3 - 6 UNDEFINED

Always read as a logic "1"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value

programmed in the Force Disk Change Register (CR17). See the Configuration section for register description.

Model 30 Mode

DSK

CHG

DMAEN NOPREC DRATE

SEL1

DRATE

SEL0

RESET

COND.

N/A

BITS 0 - 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data

rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 NOPREC

This bit reflects the value of NOPREC bit set in the CCR register.

BIT 3 DMAEN

This bit reflects the value of DMAEN bit set in the DOR register bit 3.

BITS 4 - 6 UNDEFINED

Always read as a logic "0"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value

programmed in the Force Disk Change Register (CR17). See the Configuration section for register description.

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