© 2002 QuickLogic Corporation

www.quicklogic.com

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QL4016 QuickRAM Data Sheet Rev I

Product Summary

Total of 118 I/O Pins

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110 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

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8 high-drive input/distributed network pins

Eight Low-Skew Distributed Networks

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Two array clock/control networks available to the logic cell flip-flop clock, set and reset

inputs—each driven by an input-only pin

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Six global clock/control networks available to the logic cell F1, clock, set and reset inputs

and the input and I/O register clock, reset and enable inputs as well as the output enable

contro—each driven by an input-only or I/O pin, or any logic cell output or I/O cell

feedback

High Performance Silicon

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Input + logic cell + output total delays = under 6 ns

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Data path speeds over 400 MHz

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Counter speeds over 300 MHz

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FIFO speeds over 160+ MHz