MIC28513 datasheet(16/34 Pages) MICROCHIP

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MIC28513

DS20005522A-page 16

 2016 Microchip Technology Inc.

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

Symbol

Description

Low-Side Gate Drive. Internal low-side power MOSFET gate connection. This pin must

be left unconnected or floating.

PGND

PGND is the return path for the low-side driver circuit. Connect to the source of low-side

MOSFET (PGND, pins 10, 11 22, 23, and 26) through a low-impedance path.

High-Side Gate Drive. Internal high-side power MOSFET gate connection. This pin

must be left unconnected or floating.

4, 7, 8, 9, 25

(25 is ePad)

PVIN

Power Input Voltage. The PVIN pins supply power to the internal power switch. Connect

all PVIN pins together and bypass locally with ceramic capacitors. The positive terminal

of the input capacitor should be placed as close as possible to the PVIN pins, the

negative terminal of the input capacitor should be placed as close as possible to the

PGND pins 10,11, 22, 23, and 26.

The LX pin is the return path for the high-side driver circuit. Connect the negative

terminal of the bootstrap capacitor directly to this pin. Also connect this pin to the SW

pins 12, 21, and 27, with a low-impedance path. The controller monitors voltages on this

and PGND for zero current detection.

BST

Bootstrap Pin. This pin provides bootstrap supply for the high-side gate driver circuit.

Connect a 0.1 µF capacitor and an optional resistor in series from the LX (pin 5) to the

BST pin.

10, 11, 22, 23,

(26 is ePad)

PGND

Power Ground. These pins are connected to the source of the low-side MOSFET. They

are the return path for the step-down regulator power stage and should be tied together.

The negative terminal of the input decoupling capacitor should be placed as close as

possible to these pins.

12, 21, 27

(27 is ePad)

Switch Node. The SW pins are the internal power switch outputs. These pins should be

tied together and connected to the output inductor.

AGND

Analog Ground. The analog ground for VDD and the control circuitry. The analog ground

return path should be separate from the power ground (PGND) return path.

Feedback Input. The FB pin sets the regulated output voltage relative to the internal

reference. This pin is connected to a resistor divider from the regulated output such that

the FB pin is at 0.8V when the output is at the desired voltage.

PGOOD

The power good output is an open drain output requiring an external pull-up resistor to

external bias. This pin is a high impedance open circuit when the voltage at FB pin is

higher than 90% of the feedback reference voltage (typically 0.8V).

Enable Input. The EN pin enables the regulator. When the pin is pulled below the

threshold, the regulator will shut down to an ultra-low current state. A precise threshold

voltage allows the pin to operate as an accurate UVLO. Do not tie EN to VDD

VIN

Supply voltage for the internal LDO. The VIN operating voltage range is from 4.6V to

45V. A ceramic capacitor from VIN to AGND is required for decoupling. The decoupling

capacitor should be placed as close as possible to the supply pin.

ILIM

Current Limit Setting. Connect a resistor from this pin to the SW pin node to allow for

accurate current limit sensing programming of the internal low-side power MOSFET.

VDD

Internal +5V Linear Regulator: VDD is the internal supply bus for the IC. Connect to an

external 1 µF bypass capacitor. When VIN is <5.5V, this regulator operates in drop-out

mode. Connect VDD to VIN.

PVDD

A 5V supply input for the low-side N-channel MOSFET driver circuit, which can be tied

to VDD externally. A 1 μF ceramic capacitor from PVDD to PGND is recommended for

decoupling.

FREQ

Switching Frequency Adjust pin. Connect this pin to VIN to operate at 680 kHz. Place a

resistor divider network from VIN to the FREQ pin to program the switching frequency.

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