| 전자부품 데이터시트 검색엔진 |
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PL102-10TC-R 데이터시트(PDF) 5 Page - Micrel Semiconductor |
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PL102-10TC-R 데이터시트(HTML) 5 Page - Micrel Semiconductor |
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5 / 7 page ![]() PL102-10 Low Skew Output Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 5 Output-Output Skew REF CLKOUT The skew between CLKOUT and the CLK(1-2) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will be maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must be equally loaded. If the CLK(1-2) outputs are less loaded than CLKOUT, CLK(1-2) outputs will lead it; if the CLK(1-2) is more loaded than CLKOUT, CLK(1-2) will lag the CLKOUT. Since the CLKOUT and the CLK(1-2) outputs are identical, they all start at the same time, but difference loads cause them to have different rise times and different times crossing the measurement thresholds. CLK(1-2) Zero Delay REF CLKOUT CLK(1-2) Advanced REF CLKOUT CLK(1-2) Delayed REF input and all outputs are equally loaded REF input and CLK(1-2) outputs are equally loaded, with CLK(1-2) less loaded than CLKOUT. REF input and CLK(1-2) outputs loaded equally, withCLK(1-2) more loaded then CLKOUT. |
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